{"componentChunkName":"component---src-templates-post-template-js","path":"/unix-xv6-008-kernel-main-05-en","result":{"data":{"markdownRemark":{"id":"921de312-c234-55dd-80f5-10a43c4fb749","html":"
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Inspired by An Introduction to OS Code Reading: Learning Kernel Internals with UNIX V6, I’m reading xv6 OS.

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Because UNIX V6 itself does not run on x86 CPUs, I decided to read the source of kash1064/xv6-public: xv6 OS, a fork of the xv6 OS repository that makes UNIX V6 run on the x86 architecture.

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In the previous article, I looked at how the lapicinit function called from main configures the Local APIC.

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This time, I will trace the behavior of the seginit function.

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Table of Contents

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The seginit function

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The seginit function sets the kernel segment descriptors on the CPU.

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seginit();       // segment descriptors
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The seginit function is defined in vm.c as follows.

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// Set up CPU's kernel segment descriptors.\n// Run once on entry on each CPU.\nvoid seginit(void)\n{\n  struct cpu *c;\n\n  // Map \"logical\" addresses to virtual addresses using identity map.\n  // Cannot share a CODE descriptor for both kernel and user\n  // because it would have to have DPL_USR, but the CPU forbids\n  // an interrupt from CPL=0 to DPL=3.\n  c = &cpus[cpuid()];\n  c->gdt[SEG_KCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, 0);\n  c->gdt[SEG_KDATA] = SEG(STA_W, 0, 0xffffffff, 0);\n  c->gdt[SEG_UCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, DPL_USER);\n  c->gdt[SEG_UDATA] = SEG(STA_W, 0, 0xffffffff, DPL_USER);\n  lgdt(c->gdt, sizeof(c->gdt));\n}
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Let’s read through the source code.

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First, the cpu structure was defined in proc.h as follows.

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// Per-CPU state\nstruct cpu {\n  uchar apicid;                // Local APIC ID\n  struct context *scheduler;   // swtch() here to enter scheduler\n  struct taskstate ts;         // Used by x86 to find stack for interrupt\n  struct segdesc gdt[NSEGS];   // x86 global descriptor table\n  volatile uint started;       // Has the CPU started?\n  int ncli;                    // Depth of pushcli nesting.\n  int intena;                  // Were interrupts enabled before pushcli?\n  struct proc *proc;           // The process running on this cpu or null\n};
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The cpu structure is stored in the array cpus.

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As seen in the Multiprocessor Edition, this is an array supporting up to 8 CPUs, as set by NCPU defined in param.h.

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Looking up cpus

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Let’s look at the section that retrieves the cpu structure from the cpus array.

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struct cpu *c;\nc = &cpus[cpuid()];
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The cpuid function is defined in proc.c as follows.

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It returns the value obtained by subtracting cpus from the return value of mycpu (I wonder what exactly it’s doing…).

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// Must be called with interrupts disabled\nint cpuid() {\n  return mycpu()-cpus;\n}\n\n// Must be called with interrupts disabled to avoid the caller being\n// rescheduled between reading lapicid and running through the loop.\nstruct cpu* mycpu(void)\n{\n  int apicid, i;\n  \n  if(readeflags()&FL_IF) panic(\"mycpu called with interrupts enabled\\n\");\n  \n  apicid = lapicid();\n  // APIC IDs are not guaranteed to be contiguous. Maybe we should have\n  // a reverse map, or reserve a register to store &cpus[i].\n  for (i = 0; i < ncpu; ++i) {\n    if (cpus[i].apicid == apicid) return &cpus[i];\n  }\n  panic(\"unknown apicid\\n\");\n}
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The key part of mycpu is the following code.

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apicid = lapicid();\n// APIC IDs are not guaranteed to be contiguous. Maybe we should have\n// a reverse map, or reserve a register to store &cpus[i].\nfor (i = 0; i < ncpu; ++i) {\n  if (cpus[i].apicid == apicid) return &cpus[i];\n}
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The lapicid function is defined in lapic.c; it retrieves the APICID from the Local APIC and returns it after right-shifting by 24 bits.

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int lapicid(void)\n{\n  if (!lapic) return 0;\n  return lapic[ID] >> 24;\n}
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The variable lapic holds the address of the Local APIC, which was stored in mp.c as seen in the Multiprocessor Edition.

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According to Intel’s multiprocessor specification (section 5-1), the Local APIC is placed at the base memory address 0x0FEE00000, and Local APIC IDs are assigned consecutively starting from 0 on the hardware.

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Reference: INTEL MULTIPROCESSOR SPECIFICATION Pdf Download | ManualsLib

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When I confirmed this in the debugger, the value of lapic[ID] was 0 on the first call.

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Therefore the return value of lapicid is also 0.

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This means apicid = lapicid(); stores 0 in apicid.

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I also confirmed with the debugger that cpus[i].apicid is also 0 and matches apicid, so &cpus[i] returns &cpus[0].

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for (i = 0; i < ncpu; ++i) {\n  if (cpus[i].apicid == apicid) return &cpus[i];\n}
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Therefore return mycpu()-cpus; is also 0, and I confirmed that the return value of the first cpuid call is 0.

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This means c = &cpus[cpuid()]; becomes c = &cpus[0]; on the first run.

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Setting the GDT

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So the following lines set values in the gdt[NSEGS] element of &cpus[0].

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// Map \"logical\" addresses to virtual addresses using identity map.\n// Cannot share a CODE descriptor for both kernel and user\n// because it would have to have DPL_USR, but the CPU forbids\n// an interrupt from CPL=0 to DPL=3.\nc = &cpus[cpuid()];\nc->gdt[SEG_KCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, 0);\nc->gdt[SEG_KDATA] = SEG(STA_W, 0, 0xffffffff, 0);\nc->gdt[SEG_UCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, DPL_USER);\nc->gdt[SEG_UDATA] = SEG(STA_W, 0, 0xffffffff, DPL_USER);\nlgdt(c->gdt, sizeof(c->gdt));
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&cpus[0] is the cpu structure described above, and gdt is defined as follows.

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struct segdesc gdt[NSEGS];   // x86 global descriptor table
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The segdesc structure is a structure defined in mmu.h.

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#ifndef __ASSEMBLER__\n// Segment Descriptor\nstruct segdesc {\n  uint lim_15_0 : 16;  // Low bits of segment limit\n  uint base_15_0 : 16; // Low bits of segment base address\n  uint base_23_16 : 8; // Middle bits of segment base address\n  uint type : 4;       // Segment type (see STS_ constants)\n  uint s : 1;          // 0 = system, 1 = application\n  uint dpl : 2;        // Descriptor Privilege Level\n  uint p : 1;          // Present\n  uint lim_19_16 : 4;  // High bits of segment limit\n  uint avl : 1;        // Unused (available for software use)\n  uint rsv1 : 1;       // Reserved\n  uint db : 1;         // 0 = 16-bit segment, 1 = 32-bit segment\n  uint g : 1;          // Granularity: limit scaled by 4K when set\n  uint base_31_24 : 8; // High bits of segment base address\n};
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Incidentally, NSEGS is also defined as the constant 6 in mmu.h.

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// cpu->gdt[NSEGS] holds the above segments.\n#define NSEGS     6
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The segdesc structure defined here is a segment descriptor.

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