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Inspired by An Introduction to OS Code Reading: Learning Kernel Internals with UNIX V6, I’m reading xv6 OS.

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Because UNIX V6 itself does not run on x86 CPUs, I decided to read the source of kash1064/xv6-public: xv6 OS, a fork of the xv6 OS repository that makes UNIX V6 run on the x86 architecture.

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In the previous article, I looked at the seginit function executed from main.

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This time, I will trace the behavior of picinit and ioapicinit.

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Table of Contents

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The picinit function

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The picinit function is defined in picirq.c.

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It is a very small function, as shown below.

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#include \"types.h\"\n#include \"x86.h\"\n#include \"traps.h\"\n\n// I/O Addresses of the two programmable interrupt controllers\n#define IO_PIC1         0x20    // Master (IRQs 0-7)\n#define IO_PIC2         0xA0    // Slave (IRQs 8-15)\n\n// Don't use the 8259A interrupt controllers.  Xv6 assumes SMP hardware.\nvoid picinit(void)\n{\n  // mask all interrupts\n  outb(IO_PIC1+1, 0xFF);\n  outb(IO_PIC2+1, 0xFF);\n}\n\n//PAGEBREAK!\n// Blank page.
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outb is the following function defined in x86.h.

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static inline void outb(ushort port, uchar data)\n{\n  asm volatile(\"out %0,%1\" : : \"a\" (data), \"d\" (port));\n}
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It emits assembly that sends data to an arbitrary port.

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Reference: assembly - what does “outb” in AT&T asm mean? - Stack Overflow

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Here it masks the ports 0x21 and 0xA1, which are related to the 8259 PIC.

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The 8259 PIC is an interrupt controller that accepts interrupt requests and sends them to the CPU, but xv6OS assumes SMP hardware and implements interrupts with APICs, so it has to be disabled.

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Here, both 0x21 and 0xA1 are data ports of the 8259 PIC.

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As described in the OSDev wiki below, when interrupts are implemented with the local APIC and IOAPIC, the 8259 PIC is disabled by writing 0xFF to these data ports.

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Reference: 8259 PIC - OSDev Wiki

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Reference: assembly - I/O Port Addressing - Stack Overflow

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The ioapicinit function

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The processing in picinit is now complete, and the PIC has been disabled.

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Next, ioapicinit, which is defined in ioapic.c, is called from main.

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This function initializes the IOAPIC.

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void ioapicinit(void)\n{\n  int i, id, maxintr;\n\n  ioapic = (volatile struct ioapic*)IOAPIC;\n  maxintr = (ioapicread(REG_VER) >> 16) & 0xFF;\n  id = ioapicread(REG_ID) >> 24;\n  if(id != ioapicid) cprintf(\"ioapicinit: id isn't equal to ioapicid; not a MP\\n\");\n\n  // Mark all interrupts edge-triggered, active high, disabled,\n  // and not routed to any CPUs.\n  for(i = 0; i <= maxintr; i++){\n    ioapicwrite(REG_TABLE+2*i, INT_DISABLED | (T_IRQ0 + i));\n    ioapicwrite(REG_TABLE+2*i+1, 0);\n  }\n}
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Let’s look through the code in order.

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Accessing the memory-mapped IOAPIC register region

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In the line ioapic = (volatile struct ioapic*)IOAPIC;, the variable ioapic is set to point to an ioapic structure.

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IOAPIC is defined as 0xFEC00000 in ioapic.c.

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// ioapic.c\n#define IOAPIC  0xFEC00000   // Default physical address of IO APIC
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Because the default IOAPIC address is guaranteed to be 0xFEC00000, this address is specified as a fixed value.

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Reference: x86 - About the IO-APIC 82093AA - Stack Overflow

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The ioapic structure itself is very simple:

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// IO APIC MMIO structure: write reg, then read or write data.\nstruct ioapic {\n  uint reg;\n  uint pad[3];\n  uint data;\n};
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Reference: Memory Mapped Registers for Accessing IOAPIC Registers

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Reference image: Intel 9 Series Chipset Platform Controller Hub Datasheet

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The first member, reg, is used as an index, and data is then read or written through the data area.

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I was curious about what values were actually stored in the ioapic region at boot, so I checked it in the debugger.

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I looked at 20 bytes starting at 0xFEC00000, and at this point everything was zero.

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$ x/5wx 0xfec00000\n0xfec00000:0x000000000x000000000x000000000x00000000\n0xfec00010:0x00000000
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Reading and writing data via the Data register

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Next, look at the following code.

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maxintr = (ioapicread(REG_VER) >> 16) & 0xFF;\nid = ioapicread(REG_ID) >> 24;\nif(id != ioapicid) cprintf(\"ioapicinit: id isn't equal to ioapicid; not a MP\\n\");
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The ioapicread function writes the received value to ioapic->reg, then reads and returns the value of data.

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static uint ioapicread(int reg)\n{\n  ioapic->reg = reg;\n  return ioapic->data;\n}
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In the IOAPIC, ioapic->reg is used as an index register, so data can be read and written indirectly.

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The correspondence between index values and registers is as follows.

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Reference image: Intel 9 Series Chipset Platform Controller Hub Datasheet

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Reference: I/O APICについて - 睡分不足

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The line maxintr = (ioapicread(REG_VER) >> 16) & 0xFF; gets version information by setting the index register to 1.

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$ x/5wx 0xfec00000\n0xfec00000:0x000000010x000000000x000000000x00000000\n0xfec00010:0x00170020
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maxintr becomes 0x17.

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This seems to be retrieving the MRE field in bits 23:16 of the version register.

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It looks like this value is the number of interrupt input pins minus one. (Perhaps this corresponds to the maximum number of interrupts that can be defined?)

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Reference image: Intel 9 Series Chipset Platform Controller Hub Datasheet

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In the next line, id was read as 0x0.

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This is the value in bits 27:24 of the ID register, which represents the APIC ID. (Since the first one is 0, maybe the value is 0 on the first run?)

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Reference image: Intel 9 Series Chipset Platform Controller Hub Datasheet

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It then checks whether this value matches ioapicid.

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As I saw in the multiprocessor article, ioapicid is the APIC number obtained from the MP configuration table.

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Initializing the Redirection Table

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Finally, ioapicwrite is used to disable all entries in the Redirection Table.

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// Mark all interrupts edge-triggered, active high, disabled,\n// and not routed to any CPUs.\nfor(i = 0; i <= maxintr; i++){\n  ioapicwrite(REG_TABLE+2*i, INT_DISABLED | (T_IRQ0 + i));\n  ioapicwrite(REG_TABLE+2*i+1, 0);\n}
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The ioapicwrite function writes data using the index and write value as follows.

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static void ioapicwrite(int reg, uint data)\n{\n  ioapic->reg = reg;\n  ioapic->data = data;\n}
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INT_DISABLED is defined as 0x00010000.

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This sets bit 17 to 1.

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